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Hardware
IBM P690 Regatta (Power 4 Dual Core Chip)
IBM P690 Regatta (Power 4 Dual Core Chip)
 
  IBM P690 Regatta
  NCHC P690 User Computing Environment
  IBM Compiler Command
 
Detail

IBM P690 Regatta (Power 4 Dual Core Chip) System Hardware Configuration
  1. Hostname : imp1~imp10
  2. Model Name : IBM pSeries 690 Turbo 1.3 GHz
  3. CPU :
    • Number : 32 per node ( Dual Core per Chip )
    • Model : Power 4 Chip (64 Bit)
    • Clock Rate : 1.3 GHz
    • Archtecture: SMP
    • Integer Peak Performance: SPECcint2000 : 814 ( per CPU)
    • Floating Peak Performance: SPECcfp2000 : 1266 ( per CPU )
    • Global Performance: ( Linpack )
      • Rmax : 736.6 GFLOPS ( 256 CPUs )
      • Rpeak : 1331 GFLOPS ( 256 CPUs )
  4. L1 Cache (per CPU)
    • Instruction/Data: 32KB/64KB
    • Organization: Direct map, 128-byte line(instruction)
      Two-way, 128-byte line(data)
    • Capacity : 128 KB per chip (64KB per processor)
  5. L2 Cache (per chip)
    • Size : 1.4 MB
    • Bandwidth : Shared 124.8 GB/sec
    • Organization: Eight-way, 128-byte line
  6. L3 Cache ( per MCM)
    • Size : Shared 32 MB/chip (128MB/8-way module)
    • Bandwidth : Shared 13.9 GB/sec
    • Organization: Eight-way , 512-byte line, managed as four 128-byte sectors
  7. Internal System Bandwidth: 12.8GB/sec ( x 16 = 205 GB/sec for 32-way )
  8. Main Memory:
    • Type : Shared Nothing
    • Capability : 1,024 Gbyte ( 128 GB per node )
  9. Physical Disks
    • Internal: 18 GB x 2
  10. Major Directories
    • /u1 : 100 GB
    • /u2 : 921 GB
    • /package1 : 100 GB
    • /work1: 200 GB
    • /work2: 200 GB
    • /work3: 921 GB
    • /work4: 926 GB
    • /work5: 926 GB
    • /scratch : 31 GB * 8 nodes
  11. Peripherals
    • Internal: DAT drive and DVD Ram
  12. Graphics
    • Accelerator: N/A
    • Bit-Planes: N/A
  13. Job Submission
    • Interactive: yes ( 2 hrs limits)
    • Batch: LoadLevel
  14. Installation/Upgrade Records
    • 2002/09 : install AIX 5.1L , PSSP 3.4
  15. Documentions
  16. More Information
  17. NCHC Consulting Window:
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System Software
  1. AIX 5.1 64bit version
  2. PSSP 3.5
  3. LoadLevel 3.2
  4. Fortran 77/90 8.1
  5. High Performance Fotran 1.4
  6. IBM C Language 6.0
  7. IBM C++ Language 6.0
  8. VisualAge C++ 6.0
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Application Packages
Most of application package on system are placed in /package1 directory. You may get further information for application packages list at http://www.nchc.org.tw/softwareDatabase.php


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NCHC NCHC P690 User Computing Environment

NCHC P690 Regatta Configuration
LoadLeveler Queuing System:
IBM P690 Regatta Configuration of batch classes

Disk usage Constrained Policy :
  1. /tmp : clear files not accessed over 1 day.
  2. /work1 : clear files not accessed over 1 week.
  3. /work2 : clear files not accessed over 1 week.
  4. /work3 : clear files not accessed over 2 week.
  5. /work4 : clear files not accessed over 2 week.
  6. /work5 : clear files not accessed over 2 week.
  7. /scratch : clear files not accessed over 1 day.( only apply in computing node )
NCHC reverses the right to change/reconfigure/destroy these working filesystem without any backup.


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NCHC IBM Compiler Command

  1. C for AIX Compiler Command:

    2. "xlc" , “xlc_r” , "cc" , “cc_r”...

  2. VisualAge C++ Compiler : (eg: xxx.C)

    3. "xlC" ,"xlC_r"

  3. XL Fortran for AIX :

    4. "xlf" , "f77" , "xlf_r" , "xlf90"...

  4. MPI for C :

    5. "mpcc" , "mpcc_r"

  5. MPI for C++ : (eg: xxx.C)

    6. "mpCC" ,"mpCC_r"

  6. MPI for Fortran

    7. "mpxlf" , "mpxlf90" , "mpxlf90_r"...

    example :
    Source file : run.C
    Execute file : run.exe

    mpCC -o run.exe run.C

    Detail refer to
    http://www.nersc.gov/vendor_docs/ibm/pe/am102mst02.html

  1. Compiler Options - Performance:
    1. Tyep of RS/6000 System : “–qarch=[architechture]”

      2. -qarch=pwr2 (IBM power 2 chip) [ivy system]
      -qarch=pwr3 (IBM power 3 chip) [ivory system]
      -qarch=pwr4 (IBM power 4 chip, now the compiler version did not support yet) [imp system]

    2. Tuning for specific system : “-qtune=[implementation]”

      3. -qtune= pwr2 (IBM power 2 chip) [ivy system]
      -qtune=pwr3 (IBM power 3 chip) [ivory system]
      -qtune=pwr4 (IBM power 4 chip, now the compiler version did not support yet) [imp system]

    3. Optimization Level ( -O,-O2, -O3, -O4 )

      4. Deault : no optimization

      1. -O3 is desired setting
      2. Use –qstrict ( When –O3 –qhot ) to restrict semantic alteration
      3. -O4 implied –O3 –qhot –qipa (only for wall struct)

  2. Compiler Options – Data

    1. Default Data type are 32-bit
      • REAL*4,Complex*8
      • Integer*4
      • Logical*4
    2. 64-bit Floation Poing Repersentation (-qrealsize=bytes)
      • -qrealsize=8 for double precision (64-bit)
    3. 64-bit mode ( -q64 )
    4. Specify the maximum user data area ( -bmaxdata )
      • In 32-bit mode, the default maximum user data area is 256MB.
      • -bmaxdata:0x10000000 (default)
      • -bmaxdata:0x80000000 (get eight 256MB segments, 2GB)
    5. Specify the maximum space for the program stack area
      • For automatic data area
      • -bmaxstack= to overcome soft limit on stack size
      • Maximun allowed value is 256MB for 32-bit mode

      More Detail XL Fortran info refer to
      http://www-3.ibm.com/software/ad/fortran/xlfortran/

      More Detail C Language info refer to
      http://www-3.ibm.com/software/ad/vacpp/



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